Superconducting logic is becoming denser. It is still a systems problem

Imec has demonstrated three-metal-level niobium-titanium-nitride Josephson-junction circuits at a design density of 3.8 million junctions per square centimetre, alongside three routing layers with wires reduced to a 30nm linewidth. The research matters because superconducting digital logic needs a credible route to far greater integration if it is to move beyond specialist demonstrations.

The result should not be read as a near-term replacement for CMOS processors. It is a process-platform demonstration, presented at the 2026 Applied Superconductivity Conference, and no commercial product or deployment date has been announced.

What the process result changes

Conventional niobium superconducting processes have struggled to approach the density and manufacturing infrastructure familiar to advanced semiconductor production. Imec's NbTiN work uses 300mm, CMOS-compatible process methods and reports junction diameters down to 150nm. The interconnect result is intended to support inductors, passive transmission lines, ground planes and resonators as well as logic connectivity.

That combination is more significant than a single narrow wire. A useful platform needs repeatable devices, multiple routing levels, vias, passive structures and design rules that can be used together. It must also produce data from enough wafers and structures to support models rather than isolated records.

Density does not remove the cold boundary

Superconducting logic operates at cryogenic temperatures. Any useful system therefore has to account for refrigeration, wiring into and out of the cold environment, memory, power delivery, packaging and the conversion between superconducting and conventional electronic domains.

The energy used by an individual switching event can be extremely low while the complete installation remains constrained by cooling and data movement. Claims about large efficiency or compute-density gains need to be evaluated at system level and against a defined workload.

What engineers and buyers should watch

The next evidence should include process uniformity, yield, model correlation, design-tool support, packaging options and demonstrators large enough to expose clock, power and I/O limitations. Procurement questions will eventually include foundry access, material control, cryogenic test capacity and whether a second manufacturing route exists.

Imec has framed its programme around process technology, design and EDA enablement, and system scaling through heterogeneous integration. That is the right scope. The 30nm result strengthens one part of the chain; the commercial test will be whether the chain can produce a system whose benefit survives the refrigerator.

Sources: imec, 7 September 2026, superconducting digital programme and ASC announcement.