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Imec demonstrates dense NbTiN superconducting circuits at 30nm

Imec has shown research-stage NbTiN Josephson junction circuits and 30nm superconducting interconnects aimed at future HPC, AI and quantum computing hardware.
quantum computing laboratory — illustrative stock photograph

Illustrative image: Google DeepMind on Pexels

Imec presented a three-metal-level niobium-titanium-nitride (NbTiN) Josephson junction circuit this week at the 2026 Applied Superconductivity Conference, reaching a circuit design density of 3.8 million junctions per cm2, which imec describes as a world first. Alongside this, imec demonstrated three layers of NbTiN routing with wires scaled to a 30nm linewidth.

The work is a research demonstration from imec's superconducting digital program, not a shipping product. The program targets a CMOS-compatible, 300mm-wafer-based process platform intended for joint research and development with foundries, hyperscalers and system companies.

What was shown

The Josephson junction circuits use an NbTiN/alpha-silicon/NbTiN structure with junction diameters as small as 150nm across up to three metal levels. Separately, three layers of high-density, low-loss NbTiN wiring and vias were demonstrated for use in inductors, transmission lines, ground planes and clock or power resonators. Imec states the 30nm wire linewidth is around ten times smaller than achievable with conventional niobium-based superconducting technology.

Rationale and claimed potential

Imec says conventional niobium-based superconducting technology lacks the scalability needed to realise its full potential, which its NbTiN platform is intended to address. Imec states that superconducting technology could offer up to 100 times better energy efficiency, 1,000 times higher compute density and 1,000 times greater broadcast bandwidth than current CMOS technology; these figures are imec's own projections and have not been independently verified.

Program scope

Richard Rouse, director of imec's superconducting digital program, said the effort is structured around three pillars: process technology, design and electronic design automation (EDA) enablement, and system-level scaling using 2.5D and 3D heterogeneous integration. Imec says this approach is intended to extend beyond HPC and AI into quantum control and readout, neuromorphic computing and high-resolution single-photon detection for space and biomedical applications, alongside its wider CMOS and photonics research.

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