Sofics adds 3.3 V I/O option for TSMC’s 4 nm process

Sofics has made a 3.3 V I/O option available for chips built on TSMC's N4C process, alongside a 1.8 V implementation for the N2P nanosheet process. The specialist IP is intended for designs that need to connect an advanced-node SoC or chiplet to higher-voltage devices elsewhere in a system.

That interface can be awkward when the chip's core operates at a much lower voltage than sensors, control devices or established board-level interfaces. Sofics says its 4 nm GPIO topology includes a voltage regulator and on-chip electrostatic discharge (ESD) protection, allowing 3.3 V interfacing from the core supply without a separate voltage translator in the configurations it supports.

The company also offers configurable drive strength, slew rate and power consumption. It says the I/O topologies and IP blocks are validated and available for licensing, while other variants can be derived for specific customer requirements.

For chip designers, the useful distinction is between the announced interface voltage and the chip's core voltage: this is specialised I/O IP, not a change to the underlying N4C or N2P process. Sofics has not published detailed area, leakage or qualification data in the announcement, so design teams will need the datasheets before comparing it with a conventional I/O and level-shifting approach.