Analysis

Moving the regulator beneath the processor changes where power is lost

ASE’s vertical power-delivery platform shortens the final high-current path. Its claimed routing-loss reduction describes one part of system efficiency.
Processor and motherboard, illustrative image rather than an ASE PowerSiP implementation

Illustrative image: Jonathan Borba on Unsplash

At the final stage of an AI processor’s power supply, the distance between regulator and load has an electrical cost. The rail voltage is low, the current is high, and resistance in the intervening conductors turns part of the delivered power into heat.

ASE’s expanded PowerSiP platform tackles that path by enabling thin voltage-regulator modules beneath the processor. Its packaging toolbox includes double-sided capacitor connections, exposed-terminal capacitor arrays and copper-pin integration intended to reduce impedance while fitting within the depth available behind a compute board. ASE says the vertical arrangement can reduce parasitic routing losses by at least 50%.

That percentage describes a particular loss mechanism. It does not mean that the processor, server or data centre consumes half as much electricity.

The distinction is visible in ASE’s earlier PowerSiP example. The company reported routing losses falling from 12% to 6% compared with a side-by-side arrangement, alongside current density increasing from 0.4 to 0.6 A/mm². Halving the routing loss still leaves conversion losses and the processor’s own consumption.

The underlying mechanism is straightforward. Resistive dissipation follows I²R, so lowering path resistance becomes increasingly valuable as current rises. A shorter connection can also reduce the inductance between regulator and load, although the result depends on the complete supply-and-return geometry.

Placing regulation beneath the processor makes board layout and packaging interdependent. The regulator, capacitors and interconnects must occupy space that is already constrained by compute-tray mechanics. ASE explicitly identifies module thickness and component density as requirements for this arrangement.

The useful comparison is therefore between complete power-delivery implementations operating under equivalent conditions. Routing efficiency, converter efficiency, transient response and thermal behaviour describe different parts of that comparison. ASE’s figures support the case for shortening the final high-current path; they do not establish a universal system-efficiency improvement.

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