Synopsys expands AI agents across chip design and verification workflows

Synopsys has announced a wider portfolio of engineering agents built on its Autopilot platform, extending its AI work from individual design tasks towards workflows that span verification, implementation, analogue design, manufacturing and simulation. More than 50 customer engagements are under way, with availability planned for the end of 2026.

The distinction is in how work is coordinated. Synopsys describes its AgentEngineer products as agents able to plan and carry out longer sequences of engineering tasks, supported by more focused agents. Autopilot supplies the orchestration layer, together with access to engineering context, reusable skills, memory, telemetry and governance controls.

The named tasks make the announcement more useful than a general promise of autonomous design. Synopsys lists coverage closure, software bring up, physical implementation, analogue layout migration, mask synthesis and multi die assembly among the areas being developed. Its simulation work also extends into problems such as resonance and signal integrity.

Those tasks differ greatly in what a team can safely delegate. Generating a candidate assertion or investigating a coverage gap is one matter; accepting a result at signoff is another. The practical value will depend on whether an engineer can inspect what the agent changed, reproduce the underlying tool result and retain a clear record of approval.

Synopsys says the platform can work with its own and third party models, tools and infrastructure. It also describes access controls, encryption and runtime safeguards intended to protect design data and intellectual property. Those capabilities will be important for teams whose design flow crosses suppliers and contains sensitive customer material.

The company cites customer results, including faster verification closure and higher coverage, but the figures come from selected engagements rather than a common independent benchmark. Fujitsu reports a “10–30% productivity boost in RTL code generation” using Verification AgentEngineer capabilities. It attributes that result to work including SystemVerilog assertion generation and code refactoring; it should not be read as a measured gain across every design task.

More than 50 engagements are under way with customers. Synopsys plans broader availability by the end of 2026.