Decoupling capacitors: why placement deserves as much attention as capacitance
The distance between a decoupling capacitor and an IC is easy to judge on a layout. The electrical length of the connection is less obvious, particularly when the return takes a narrow track to a distant via or the package reaches its supply through a more complicated network underneath.
That is how a capacitor can look well placed while contributing less than expected during a fast load change. Its nominal value still matters, but the voltage at the device also depends on the pads, vias, planes and package connections carrying the current. Following that complete route gives a more useful explanation of supply noise than distance alone.
The voltage budget begins at the device
Individual rails, analogue supplies, reference pins and internal regulator outputs can have different requirements. The manufacturer’s recommended network establishes the starting conditions, including any minimum capacitance or stability limits that apply to a particular connection.
Analog Devices’ MT-101 describes how supply rejection varies with frequency. Good rejection of slow supply variation does not establish equivalent performance at higher frequencies, and the allowed voltage variation at the device has to accommodate DC error, ripple and noise together. [1]
An impedance target helps connect that voltage budget to changes in load current. For an illustrative allocation of 20 mV to a 200 mA load change:
Ztarget = ΔV / ΔI = 0.020 / 0.200 = 0.10 Ω
The frequency range is essential to interpreting that number. The regulator, bulk storage, local capacitors, planes and package respond over different timescales, so the target has to be associated with the disturbance being considered and the voltage allowance remaining after other errors.
Connection inductance changes the mounted behaviour
A capacitor’s equivalent series inductance is only one contribution to the installed circuit. AMD’s PCB guidance includes lands, traces, vias and planes in the mounted inductance and explains how mounting geometry changes effective resonance. [2]
A simple sensitivity calculation shows why even a small inductance can matter. If 1 nH carries a current change of 100 mA in 1 ns:
V = L × di/dt = 1 nH × 0.1 A / 1 ns = 0.10 V
That is a lumped illustration rather than a prediction for a particular IC. The actual transient also depends on the package and distributed network, but the result shows how connection geometry can consume a significant fraction of a tight voltage budget.
The loop includes the route from the capacitor to the supply pin and the connection back to its other terminal. A short supply trace can therefore coexist with a poor overall connection when the return is long or narrow.
For a leaded package, a capacitor on the same side with short supply and return connections may offer a useful arrangement. A large BGA presents different access constraints, where closely coupled planes and appropriately positioned vias can matter more than the distance between outlines on the component layer. The package’s recommended supply network helps distinguish these cases.
Effective capacitance can be lower than the BOM value
Ceramic capacitors with high permittivity can lose effective capacitance under DC bias. Murata documents this behaviour and provides characteristics for individual parts, allowing the expected operating voltage to be considered alongside temperature, tolerance and ageing where applicable. A single derating percentage cannot describe every package, voltage rating and construction. [3]
This becomes especially relevant during component substitution. Two parts marked 10 µF may provide different effective capacitance in the same circuit, and a regulator or reference may depend on a particular range of capacitance and ESR. Whether a minimum requirement refers to nominal or effective capacitance changes the comparison considerably.
A substitute can therefore match the purchasing description while still needing an electrical review at the intended operating point.
Combining values can introduce impedance peaks
A network containing 10 µF, 1 µF and 100 nF can cover useful frequency regions, but the branches also interact through their interconnect inductances. Those interactions can produce impedance peaks as well as low impedance regions. AMD’s guidance on antiresonance explains how capacitor characteristics, parasitic inductance and planes contribute to the combined response. [5]
Damping and mounting assumptions consequently matter when comparing a model with the board. The appropriate depth of analysis depends on the supply: a demanding FPGA rail may justify detailed modelling, while a modest microcontroller circuit may be adequately assessed through the device guidance, layout review and representative measurements.
Measurements tie the layout to the load event
A quiet regulator output does not necessarily describe the voltage at a device several centimetres away during a fast current change. A measurement near the affected supply connection, with known probe loading and bandwidth, is better placed to capture that behaviour.
The operating event also matters. A radio burst or processor workload transition can expose a disturbance that is absent at idle, and repeating that same event makes capacitor and layout changes easier to compare. Short probe connections reduce pickup and inductive measurement artefacts, although the probe’s loading still needs consideration. [4]
With that capture beside the layout, a proposed change can be related to a particular part of the network. Moving a capacitor may shorten the loop, changing the part may improve its effective capacitance or neither may address the observed disturbance. The measured rail behaviour helps establish which explanation fits.
