UMC and AP Memory take package-level silicon capacitors into testing
UMC and AP Memory have completed tape-out and initial wafer validation of silicon capacitors designed for integration closer to advanced computing devices. Their S-SiCap Gen2D discrete designs reached that milestone in the third quarter of 2026, combining UMC’s deep trench capacitor process and manufacturing with AP Memory’s design and integration work.
Testing now moves into substrate packages.
That is where the electrical promise has to survive the physical implementation. Placing capacitance closer to a computing die shortens the current path and reduces the parasitic inductance associated with more distant decoupling. The package must also provide a reliable way to manufacture and connect those capacitors.
System performance and reliability testing are the next steps. The collaboration’s longer roadmap includes capacitor-embedded interposers and landside capacitors, extending the work beyond the discrete designs validated so far.
