Crystal oscillator start-up margin: load capacitance, ESR and negative resistance
A Pierce oscillator must build oscillation from noise before the firmware's clock-start deadline. Correct frequency during steady operation does not establish that start-up margin. The crystal's equivalent series resistance, the oscillator's negative resistance and the applied load all affect whether it starts reliably.
The capacitance seen by the crystal
A Pierce oscillator combines the MCU's amplifier, the crystal and the surrounding capacitance. The crystal's specified load capacitance is the effective load presented by that circuit, not the value printed on each external capacitor.
For the usual two-capacitor approximation:
CL ≈ C1C2 / (C1 + C2) + Cstray.
The stray term represents the effective contribution of the pins, PCB and associated parasitics. With equal capacitors, the series contribution is half the value of either capacitor. Two 12pF capacitors therefore contribute approximately 6pF before parasitics are added, rather than presenting a 12pF load.
The exact calculation depends on how the device documentation defines its internal capacitance. Some MCUs include programmable load capacitors. Those values must be accounted for before external capacitance is added.
Start-up requires gain as well as the right frequency
The crystal loses energy through its effective resistance. The oscillator's active circuit must supply enough energy to overcome that loss and allow oscillation to build from noise. Negative resistance is a way of expressing the active circuit's contribution.
Microchip's guidance describes a margin comparison between oscillator negative resistance and crystal ESR. Its negative-resistance test adds resistance in series with the crystal to find the point at which start-up no longer occurs reliably. That result must be interpreted using the relevant device's procedure and acceptance criterion; one multiplier cannot be assumed to apply to every MCU and crystal combination.
Start-up and steady running are different tests. A circuit that continues oscillating after resistance is added has not necessarily demonstrated that it can start with that resistance already present. Power must be reapplied as the specified procedure requires.
Epson also identifies insufficient negative resistance as a cause of extended start-up time or failure to oscillate. Increasing oscillator drive may improve margin, but the crystal's maximum drive level still applies. Excessive drive can shift frequency or damage the resonator.
Validate the assembled circuit
The useful test range follows the finished product's voltage and temperature limits, including the MCU's oscillator settings and the crystal's maximum specified ESR. Record start-up time as well as eventual oscillation, because firmware may wait only a defined interval before declaring the clock ready.
Measurement itself can change the circuit. Probe capacitance added directly to a crystal pin becomes part of the load, especially in a low-power 32.768kHz oscillator. Use the manufacturer's recommended measurement arrangement or a suitable buffered clock output, and document the probe loading when direct measurement is unavoidable.
If firmware reports a start-up failure while the clock eventually appears on an instrument, the two observations need not conflict. The oscillator may be building amplitude too slowly for the configured timeout. Start-up time, supply and temperature conditions therefore belong alongside the final frequency measurement.
