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AnalogAI licenses SST memBrain IP for edge AI chips

AnalogAI has licensed Microchip subsidiary SST's memBrain SAGE analog compute-in-memory IP for edge AI processors aimed at robots, drones and vehicles.
Microchip Technology official press image accompanying the announcement

South Korea-based AnalogAI has selected memBrain Synaptic Analog Generative Engine (SAGE) hardware intellectual property from Silicon Storage Technology (SST), a Microchip Technology subsidiary, as the inference engine for its first edge AI processors. The chips are designed to train and run inference simultaneously on-device, adapting AI models to changing real-world conditions.

Analog compute-in-memory IP

SST's memBrain SAGE IP implements analog compute-in-memory (aCIM), built on SST's SuperFlash embedded flash technology. According to Microchip, the IP block includes:

  • A Tensor In-Memory Logic Element (TILE) with an ESF3 bitcell storing up to 8 bits per cell at nanoamp levels
  • Custom array, decoder and driver circuitry, plus optimised DACs and ADCs
  • Summator and high-voltage bias circuitry, and nanoamp-level bitcell control logic
  • Proprietary test circuitry, documentation, simulation models and IP integration support

Microchip states the memBrain SAGE IP has been developed and deployed in 40nm and 28nm foundry processes using production-ready SuperFlash memory, with a 22nm version on its roadmap. AnalogAI says it selected the IP after an industry-wide evaluation, citing silicon-proven status as a factor in accelerating development.

Target applications and claims

AnalogAI describes its architecture as combining on-device training and inference in a single low-power design, intended for humanoid robots, drones and vehicles that must adapt after deployment. Microchip and AnalogAI state the approach targets aCIM performance at or below one watt for ultra-low-power edge applications; this is a vendor claim rather than an independently verified figure. No product launch date, process node for AnalogAI's own chip, or shipping timeline was disclosed in the announcement, which concerns an IP licensing arrangement rather than a released product.

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