Orthogone opens low-latency FPGA networking IP to wider industries
Orthogone Technologies has released a portfolio of FPGA networking and data-movement IP for AMD UltraScale+ and Versal adaptive platforms.
The Canadian engineering company originally developed the technology for financial trading systems, where deterministic behaviour, low latency and low jitter are central requirements. It is now offering the IP for aerospace, industrial automation, robotics, medical equipment, communications, high-performance computing and test systems.
The portfolio includes Ethernet MAC/PCS cores supporting 1, 10, 25, 40 and 100Gbit/s line rates. Reed-Solomon forward error correction is available for 25 and 100Gbit/s operation.
Hardware TCP/IP and UDP/IP engines move Layer 2 to Layer 4 packet processing into FPGA logic. Orthogone says this reduces the networking workload placed on the host processor and supports sub-microsecond-class data paths. Exact latency will depend on the selected core, FPGA implementation and system configuration.
A circular-buffer DMA controller provides bidirectional transfers between the host and FPGA over PCIe Gen3 or Gen4.
The development kit includes encrypted RTL source, AMD Alveo reference designs, simulation testbenches, Linux drivers and documentation. Licensing is available by project, site, company, annual subscription or individual card.
Orthogone says the IP has already been used in production systems, although the release does not provide independently verified comparative benchmarks. Evaluation and commercial licensing are available now.
