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Winbond targets 8 GB/s at around 70 mW with CUBE-Lite memory

The semi-custom memory is aimed at compact AI devices, with a simpler controller interface and production targeted for the first half of 2027.
Integrated circuits and PCB tracks in a monochrome macro photograph. Illustrative image, not CUBE-Lite hardware.

Illustrative image: Unsplash contributor on Pexels

Winbond has announced CUBE-Lite, a semi-custom memory solution targeting up to 8 GB/s of bandwidth at approximately 70 mW. The company quotes access latency of about 20 ns and is validating the product ahead of a planned move to mass production in the first half of 2027.[1]

The intended applications include wearable devices, AI image processing and microcontroller-based systems, where local inference has to share a limited power and thermal budget with the rest of the electronics. CUBE-Lite extends Winbond’s customised CUBE memory strategy towards smaller endpoints, prioritising low power and simpler integration over the highest bandwidth configurations.[1][2]

AI processing repeatedly moves model data and intermediate results between memory and compute. Winbond’s architectural material describes the cost of increasing that traffic through conventional interfaces: wider connections consume more pins and routing space, while higher data rates increase switching losses. Bringing the memory closer can shorten connections, although it also places demands on packaging and heat removal.[2]

CUBE’s wider platform supports several integration routes, including chip-on-wafer and wafer-on-wafer structures, as well as 2.5D and 3D packaging. Through-silicon vias are an option within that broader technology. Winbond is working with foundries, packaging companies and ASIC partners around the architecture, making the memory interface part of the system integration work rather than an isolated board-level component choice.[2][3]

For CUBE-Lite, the supplier separately claims more than a tenfold reduction in SoC controller power against an LPDDR4x implementation, together with reduced interface circuitry area. The 70 mW memory figure and that controller comparison describe different parts of the system; combining them into a single percentage saving would require the complete reference configurations and workloads.[1]

At the quoted peak transfer rate, 70 mW divided by 64 billion bits per second gives roughly 1.1 picojoules per bit, consistent with the company’s rounded figure of about 1 pJ/bit. This calculation describes transfer energy at that operating point, with the power consumed by the AI processor and other system functions additional. [1]

Integrated circuits and PCB tracks. Illustrative photograph. Photo: Sergei Starostin / Pexels. Image source. Reuse terms.

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