Weebit’s ReRAM kit puts analogue computing on the bench

Weebit Nano has opened its Matrix research programme around a ReRAM chip with a 32 × 32 crossbar, offering researchers hardware for investigating computation inside memory. One package provides a direct-access evaluation board; another adds an FPGA subsystem and sample code, with both including chip samples, documentation and a socketed board.^[1]

AI inference repeatedly applies stored weights to incoming values, multiplying and adding them to produce the next set of results. Moving those weights between memory and a processor consumes energy before the arithmetic has even started, particularly when the same model is applied repeatedly to a stream of sensor data. An analogue memory array can represent those weights as electrical conductances, apply the input as voltages and collect the resulting currents. Many operations then happen together in the physical array, while the weights stay where they were stored.^[2]

ReRAM provides that programmable resistance through a thin switching layer between electrodes. Weebit’s oxide-based cell changes its conductive state when voltages are applied, retaining the programmed state without continuous power. Switching between high and low resistance states stores a data bit, while using resistive devices for computation requires mathematical values to be mapped onto the array’s electrical behaviour.^[3]

With the right mapping, current flowing through a cell represents a multiplication and the combined current along an output line represents a sum. Keeping the weights in place removes the repeated fetch from a separate memory during those operations. The result is still an analogue signal, though, and a digital system needs it converted into numbers before the next processing stage can use it. Converters, sensing circuits and control logic consume energy and occupy chip area around the array.^[2][4]

IBM’s research on RRAM accelerators identifies that conversion as a source of extra power, area and accuracy loss. Its 2023 work explored a hybrid approach that added a precise digital contribution to compensate for errors in the analogue result. That hybrid approach spends additional circuitry and processing on recovering precision after the parallel analogue operation, including work that disappears from a comparison confined to the memory cells.^[4]

Poorly matched input voltages, programmed conductances and readout circuitry can lose useful information even when the array performs its electrical operation, making calibration part of obtaining a reliable numerical result. IBM’s later work investigated adjusting each crossbar’s column conductance range and input digital-to-analogue converter range after training, reducing the amount of detailed hardware information needed during training in its reported experiments.^[5]

Hardware-aware training allows a neural network to encounter representations of those imperfections during optimisation, rather than discovering them only when ideal software arithmetic meets a physical device. A demanding accuracy target can therefore change the amount of conversion and compensation required, with consequences for the energy saving available from the array.^[4][5]

A 64 × 64 matrix contains four 32 × 32 blocks, so using the smaller array for that calculation requires blocks or successive operations and the combination of partial results. Larger workloads add sequencing and data movement around the computation, making the surrounding digital work part of the performance question. ^[1][4]

Weebit will review research proposals before granting access and plans to demonstrate the platform at electronica. Its stated subjects include multiply-accumulate operations, convolution and spiking neural networks, with participants feeding findings back into development. The company also cites a partner’s projection of much lower power than a GPU for a particular workload; that remains a projection, while the kit provides a route to test actual behaviour, including where precision or peripheral circuitry changes the result.^[1]

Weebit Matrix in memory computing kit boards. Image: Weebit Nano. Image source. Reuse terms.