Wafer-scale p-type boron carbon nitride advances complementary 2D logic

A research team led by the University of Tokyo has produced wafer-scale p-type boron carbon nitride and used it to fabricate atomically thin transistors. The result addresses a persistent problem in two-dimensional electronics. Several 2D materials have demonstrated useful n-type behaviour, in which electrons carry the current, but producing a scalable p-type semiconductor with comparable performance has been more difficult. Complementary logic requires both types. An n-channel transistor pulls an output in one direction, while a p-channel device pulls it in the other. Pairing them allows CMOS circuits to draw relatively little static power. Introducing carbon into boron nitride Hexagonal boron nitride is widely used as an insulating layer in experimental 2D devices. The researchers introduced carbon into the material to create boron carbon nitride with p-type semiconductor behaviour. They reported room-temperature hole mobility of around 100cm²/Vs, drive current close to 0.9mA per micrometre of channel width and an on/off current ratio of approximately 10 8 . The reported threshold voltage was about -0.45V. Those figures were obtained from experimental devices and should not be treated as production-process specifications. Contact resistance, wafer uniformity, long-term stability and integration with other materials will determine whether similar performance can be maintained in larger circuits. Why wafer scale matters Many promising 2D devices begin with small flakes isolated mechanically from a bulk crystal. That method is useful for laboratory experiments but unsuitable for repeatable semiconductor manufacturing. The researchers instead demonstrated the material across a two-inch wafer and reported electrical distributions from 224 devices across three growth batches. This provides a route towards patterned device fabrication rather than relying on individually selected flakes. The material’s atomic thickness could be useful in monolithic three-dimensional integration, where additional transistor layers are fabricated above completed circuitry. Thin layers can reduce the vertical dimensions, although practical integration would still require compatible deposition, patterning, contacts and interconnects. Complementary devices remain the next step The reported work demonstrates the p-type half of a possible complementary platform. A complete logic technology would require the BCN devices to be combined with suitable n-type transistors and manufactured with repeatable threshold voltages and yields. The University of Tokyo work therefore resolves one material problem rather than demonstrating a finished logic process. Its significance lies in combining p-type electrical performance with a route towards large-area material growth.