Agilex 27 gives data movement more room in the FPGA

Altera’s Agilex 27 architecture moves more of the traffic between memory, interfaces and processing onto hardened interconnect. That leaves fewer transport functions competing with application logic for programmable resources, a practical change on devices expected to handle very wide data paths.

The family leads Altera’s new Agilex 2X portfolio. Early access software support is due in mid-November 2026, but engineering samples are not expected until the second half of 2027. There is time to explore the architecture in software before silicon is available to test interface behaviour, power consumption and thermal margins.

Moving the traffic out of programmable logic

HyperFlow combines a hardened network around the device’s periphery with a distributed network alongside its internal memory columns. Altera describes 512-bit network ports and dedicated data movers connecting resources including PCIe, external memory and the processor subsystem. Transfers can therefore avoid some of the buses, bridges and buffering that would otherwise occupy programmable resources.

An FPGA can have plenty of logic left and still be difficult to route because a handful of wide, busy connections constrain placement. In a capture system, for example, a continuous stream may be written to memory before selected records are sent to a host. The arithmetic can be modest while the repeated movement of those bytes dominates the implementation. Hardening some of that transport could ease the routing burden and, in some designs, reduce the device capacity needed.

Even with a hardened path, several clients can still contend for the same memory channel and unnecessary transfers will continue to waste bandwidth.

The fabric is changing too. Third-generation HyperFlex provides additional opportunities for retiming and pipelining, while revised logic packing is intended to fit more work into the device. Altera reports a 1.8-fold improvement in performance per watt over the previous generation. How much of that reaches a complete board will depend on its workload and the power consumed outside the fabric, so the figure cannot be applied directly to board throughput.

The interface numbers need a complete route behind them

The announced connectivity extends to 256 Gb/s transceivers, 1.6 Tb Ethernet and PCIe 7.0, alongside newer memory interfaces. The useful traffic rate will depend on how protocol overhead, memory access and processing interact when those interfaces are active together.

For example, a hypothetical 1.6 Tb/s stream represents 200 GB/s before overhead. Writing every byte to external memory and reading it back once would require 400 GB/s of aggregate memory traffic, before accounting for anything else using that memory. This illustrative calculation is not an Agilex benchmark. It shows how a stream that fits the external interface can create a much larger requirement inside the memory system.

Altera’s software documentation includes network congestion analysis and tools for choosing endpoints and placement. Early access could expose a congested path in a representative workload while partitioning is still open to change. The later engineering samples will have to establish the physical operating margin, from interface behaviour to power and cooling under sustained traffic.

Sources

• Altera: Agilex 2X announcement
• Altera: Agilex 27 product overview
• Altera: Agilex 27 architecture white paper, especially pages 7–8

Image: Abstract digital circuit illustration. This is not an Agilex device or die photograph. Photo: Pachon in Motion / Pexels. Image source. Licence.