VeriSilicon adds dedicated graphics engines for wearable interfaces
VeriSilicon has introduced GCNanoOptimaV, a graphics IP core for wearable devices that adds dedicated engines for drawing strokes and ellipses, alongside changes to rendering and image compression. The company says the IP has already been adopted by several customers, although it has not named them. [1]
The core targets the graphical interfaces used by devices such as watches, where curves, text and compact visual indicators have to be drawn within a limited processing and memory budget. Its stroke engine accelerates lines and curves, while a mesh rendering architecture is intended to reduce the amount of SRAM on the chip required. VeriSilicon has not published numerical comparisons for those performance and memory claims. [1]
By handling repeated drawing operations in dedicated engines, the architecture can spare a CPU from constructing each curve in software. For an interface containing animated indicators, the division of work also affects how much intermediate data is stored and retrieved, connecting the renderer with the memory needed around it. [1][2]
GCNanoOptimaV sits in the Vivante 2.5D range for microcontrollers and application processors. Here, 2.5D describes an embedded graphics family, rather than the silicon packaging technique that uses the same term. The portfolio supports RTOS and Linux environments, with the standard GCNanoOptimaV listed for displays up to 720p and a separate XR variant covering higher resolutions. [2]
The IP is integrated into a customer's SoC, with VGLite providing the software interface to its vector graphics capabilities. VeriSilicon's family comparison lists eight tessellation units and a pixel rate of one pixel per cycle for the standard core, alongside a choice of other cores with different rendering resources and API support. [2]
For the new announcement, DECNano 3.0 supplies image compression at a fixed 2:1 ratio, with VeriSilicon claiming improved image quality. Support for LVGL, SVG and PNG retains existing routes for constructing embedded interfaces and supplying their visual assets. [1]


