How Wiwynn combines vertical power delivery with chip cooling
Image: Wiwynn. Existing cold-plate assembly, illustrative, not the 6kW prototype. Reuse permission pending.
Wiwynn's double-sided cold plate combines cooling with cavity PCBA and vertical power delivery in a processor assembly rated by the company for 6kW cooling. Moving regulators beneath the chip shortens the current path, but also puts the regulator circuitry, board cavities and cooling hardware into the same volume.
The company claims more than 15% thermal improvement and up to 80% lower power-delivery loss for the OCP design. It does not give the comparison conditions behind those percentages. Separate technical studies provide more detail about two of the underlying design choices, although their results describe different comparisons.
Vertical power delivery places the voltage regulators beneath the chip rather than around its perimeter. Wiwynn's separate technical summary describes high-density via arrays and PCB cavities that shorten the current path. For a given current, reducing path resistance lowers the electrical loss according to P = I²R.
That electrical benefit becomes increasingly valuable as current rises. It also changes where regulator losses occur and how the board is constructed. Cooling access, cavity geometry and the vertical interconnect therefore have to be designed together.
Wiwynn's vertical-power-delivery study reports 20µΩ measured transmission impedance and 23.4µΩ in simulation, with a 37.1% reduction in transmission loss against its non-cavity comparison. That 37.1% result does not measure the same comparison as the OCP claim of up to 80% lower power-delivery loss.
Tailoring the channels to the heat map
A cold plate has to remove heat without demanding an impractical pressure difference from the coolant loop. Packing channels more tightly can improve heat transfer while increasing resistance to flow. The most useful geometry depends on where the heat is generated, as well as how much coolant is available.
Wiwynn's published microchannel-study summary uses a uniform 80/80µm wall-and-gap configuration as its baseline. At a fixed 50% open-area ratio, finer configurations produced a sharp rise in pressure drop for limited additional thermal benefit.
Its alternative divides the plate into five regions, retaining a higher channel density near the main hotspot and reducing it elsewhere. The reported comparison lowers pressure drop by 29.4% while reducing maximum case temperature by 0.2°C. The emphasis is on redistributing cooling effort across a non-uniform heat map, rather than simply adding more channels everywhere.
The small temperature change matters alongside the much larger pressure-drop reduction. In that study, the revised channels preserve the thermal result while requiring less pressure to drive the flow. The board-cavity work instead reduces the resistive path carrying current into the package. Combining the two in one processor assembly requires the electrical and cooling geometry to be resolved together; the published studies do not quantify that combined result.
