An AI chip that keeps its boot code and weights in embedded MRAM

Tohoku University and AISIN have built a 16 nm AI system on chip with 32 MB of embedded STT-MRAM holding boot data and neural-network weights. In their comparison, power-on to kernel startup fell from 2,535.3 ms to 65.7 ms. Object-detection processing was measured separately at 58.5 ms, with Tiny YOLOv3 consuming 50.7 mJ per frame. The boot figure therefore does not describe the time to a completed detection. ^[1]

Keeping data on the chip changes what has to happen after power is restored. Code and weights are already present, so the system avoids the external-memory transfers associated with loading them. The processor still has work to do before it can produce a useful result.

What the magnetic memory keeps

An STT-MRAM cell stores its state in a magnetic tunnel junction. A thin insulating barrier separates a reference magnetic layer from a free layer whose magnetisation can be switched. Their relative alignment changes the junction’s resistance, allowing the stored state to be read electrically. Because the information resides in that magnetic alignment, it can survive removal of the supply. Imec describes this structure in its published work on perpendicular magnetic tunnel junctions. ^[2]

That removes a reason to keep a memory powered, although it does not make the rest of a sleeping system consume nothing. A wake detector, regulator and whatever circuitry must remain responsive still draw current. Equally, retaining code does not preserve every peripheral’s configuration or guarantee that a sensor is ready to deliver a valid sample as soon as the processor starts.

A simple duty-cycle calculation shows why those details matter. Suppose an instrument wakes once a minute and needs 100 ms of useful processing. If startup adds 2.5 seconds, its active interval becomes 2.6 seconds, or about 4.3% of the minute. With a hypothetical 70 ms startup, that interval becomes 170 ms, about 0.28%. These are illustrative timings, not measurements of the Tohoku device, and they assume the same useful workload. They show how startup can dominate the time spent awake without establishing a corresponding battery-life improvement, which would also require power measurements in each state.

Fitting the model is part of the result

The researchers combined 8-bit and 16-bit multiplication and reduced weight storage from 17.7 MB to 9.36 MB. That is approximately 47% less storage. Reported mean average precision also moved from 0.325 to 0.316, so the smaller representation carries a measurable accuracy cost. ^[1]

With a finite memory budget, adding another model can change the architecture rather than merely occupy spare storage. If the required code, weights and other data no longer fit, external memory may return to the design, together with its loading sequence. The same applies if a more accurate representation needs substantially more space.

This remains a research prototype. The published result establishes a particular object-detection implementation, rather than a general performance claim for much larger models. Production qualification, memory retention and endurance limits would need their own specifications before the device could be selected for a long-life product.

Sources

• Tohoku University and AISIN, research announcement and measured results, 2 November 2026 (Japanese)
• Imec, magnetic tunnel junction structure and STT-MRAM operation (background)

Image: Illustrative electronics photograph, not the Tohoku University and AISIN prototype or an identified MRAM device. Credit: Ivan Chumak / Pexels. Image source. Pexels licence.