Synaptics gives its SR200 MCUs a much larger working memory
Up to 8 MB of SRAM and hundreds of megabytes of custom DRAM give Synaptics’ Astra SR200 family an unusual memory provision for an MCU platform. The capacity comes from a package containing multiple dies, integrating compute, memory and power management.
That arrangement changes the scope of the device. A camera pipeline, neural network and display can place very different demands on memory, even when their processing requirements appear manageable. Image buffers and intermediate results consume space; moving them between processing engines consumes bandwidth and energy. More accelerator throughput cannot resolve a memory bottleneck on its own.
Synaptics has divided the family into three tiers. The SR210 targets voice and sensing with up to 200 GOPS. The SR230 adds vision and display capability at up to 300 GOPS, while the SR250 extends to dual-vision and display applications at up to 400 GOPS.
Chief product officer Vikram Gupta describes the ambition as bringing “applications-processor capability into the MCU domain”. Those performance figures are Synaptics’ stated capabilities for the respective products, rather than results from a common application benchmark.
Keeping the data close
The architecture connects the CPU, DSP and neural processor to shared memory banks through a wide internal fabric. Custom DRAM supplies capacity beyond the SRAM provision, with an interface designed around the package.
Synaptics compares aspects of the arrangement with HBM. It is an architectural analogy, rather than a statement that the SR200 contains a conventional JEDEC HBM stack. The relevant question is how effectively the processing engines can share data without repeatedly copying it between separate resources.
Around that memory sit an Arm Cortex-M85 running at up to 800 MHz, a Cortex-M52 at up to 200 MHz and an optional HiFi 5 DSP. Family capabilities include dual MIPI CSI-2 camera interfaces and display configurations extending to one 1080p output at 60 frames per second or two at 30 frames per second. The available combination depends on the device selected.
The power architecture deserves as much attention as the peak figures. Four domains divide always-on functions from progressively more demanding processing, allowing the active resources to change with the workload.
That suits an application which spends much of its time monitoring a modest input, then briefly needs camera processing, inference and a display. Keeping the entire machine awake for the monitoring phase would undermine the integration argument.
There is still an energy cost to retaining and accessing a large memory. The eventual balance will depend on the workload’s duty cycle and data movement. The SR200 provides a more integrated place to manage those demands, with considerably more memory available before an external system architecture becomes necessary.
