SEALSQ prepares quantum-resistant chip demonstrations for electronica

SEALSQ will demonstrate two quantum-resistant security chips and a custom ASIC design concept at electronica 2026, covering secure elements, trusted platform modules and application-specific silicon.

VaultIC409 is based on the company’s QS7001 platform and combines an SPI interface with a hardware root of trust and support for the ML-KEM and ML-DSA post-quantum algorithms. The device is undergoing Common Criteria EAL5+ certification, with engineering samples expected in the second quarter of 2027.

The QVault TPM is intended to keep post-quantum keys within the chip while retaining RSA and elliptic-curve cryptography support. Its certification programme includes FIPS 140-3 and Trusted Computing Group requirements.

SEALSQ will also present QASIC, a post-quantum ASIC design offering involving IC’Alps. This is a custom development proposition rather than a newly available catalogue component.

Software integration includes wolfTPM support within wolfSSL’s embedded security portfolio. The demonstrations will take place in Hall C6, booth 670, at the Munich exhibition from 10 to 13 November. [Source 1]