Verification / Senior Verification Engineer
Own RTL verification plans, UVM testbenches and coverage for Riverlane quantum error-correction hardware.
The role
Riverlane is recruiting a Verification or Senior Verification Engineer in Cambridge for its quantum error-correction hardware.
The role owns verification plans for block-level and system-level designs, develops SystemVerilog testbenches with UVM or OVM, implements assertions and coverage, and maintains regression and bug tracking. It also involves debugging across RTL, simulation and hardware.
The role is permanent and hybrid, with part-time applications considered. Riverlane lists £60,000 to £88,000 a year plus bonus and benefits, and states that it does not use closing dates.
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